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M51996AP/AFP
Switching Regulator Control
REJ03D0836-0201 Rev.2.01 Nov 14, 2007
Description
M51996A is the primary switching regulator controller which is especially designed to get the regulated DC voltage from AC power supply. This IC can directly drive the MOS FET with fast rise and fast fall output pulse and with a large-drive totempole output. Type M51996A has the functions of not only high frequency OSC and fast output drive but also current limit with fast response and high sensibility so the true "fast switching regulator" can be realized. The M51996A is equivalent to the M51978 with externally re-settable OVP (over voltage protection) circuit.
Features
500kHz operation to MOS FET Output current : 1 A Output rise time 60 ns, fall time 40 ns Modified totempole output method with small through current Compact and light-weight power supply Small start-up current : 100 A typ. Big difference between "start-up voltage" and "stop voltage" makes the smoothing capacitor of the power input section small. Start-up threshold 16 V , stop voltage 10 V Packages with high power dissipation are used to with-stand the heat generated by the gate-drive current of MOS FET. 14-pin DIP, 16-pin SOP 1.5W (at 25C) * Simplified peripheral circuit with protection circuit and built-in large-capacity totempole output High-speed current limiting circuit using pulse-by-pulse method (CLM+pin) Over-voltage protection circuit with an externally re-settable latch (OVP) Protection circuit for output miss action at low supply voltage (UVLO) * High-performance and highly functional power supply Triangular wave oscillator for easy dead time setting SOFT start function by expanding period * * * * *
Application
Feed forward regulator, fly-back regulator
REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 1 of 35
M51996AP/AFP
Recommended Operating Conditions
Supply voltage range: 12 to 30 V Operating frequency: less than 500 kHz Oscillator frequency setting resistance T-ON pin resistance RON: 10 k to 75 k * T-OFF pin resistance ROFF: 2 k to30 k * * * *
Block Diagram
REG (7.8 V)
7.1 V
F/B
VCC
Voltage regulator
5.8 V
3k 1S
500 6S
15.2 k
Under voltage lockout
-
OP AMP
DET
1S
1S
+
2.5 V
OVP
Latch
PWM Comparator
PWM latch
Collector VOUT
CF T-ON T-OFF Oscillator (triangle)
Current limit detection
Emitter
SOFT
CLM+
GND
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M51996AP/AFP
Pin Arrangement
M51996AP Collector VOUT Emitter OVP F/B DET REG
1 2 3 4 5 6 7 14 13 12 11 10 9 8
VCC CLM+ GND T-OFF CF T-ON SOFT
(Top view) Outline: PRDP0014AA-A (14P4)
M51996AFP Collector VOUT Emitter Heat sink pin OVP F/B DET REG
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
VCC CLM+ GND Heat sink pin T-OFF CF T-ON SOFT
(Top view) Outline: PRSP0016DE-A (16P2N-A) Note: Connect the heat sink pin to GND.
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M51996AP/AFP
Absolute Maximum Ratings
Item Supply voltage Collector voltage Output current VREG terminal output current SOFT terminal voltage CLM+ terminal voltage DET terminal voltage OVP terminal current F/B terminal current T-ON terminal input current T-OFF terminal input current Power dissipation Thermal derating Operating temperature Storage temperature VCC VC IO IVREG VSOFT VCLM+ VDET IOVP IFB ITON ITOFF Pd K Topr Tstg Symbol Ratings 31 31 1 0.15 -6 VREG + 0.2 -0.3 to +3 6 10 -10 -1 -2 1.5 12 -30 to +85 -40 to +125 Unit V V A mA V V V mA mA mA mA W mW/C C C Ta = 25C Ta > 25C Peak Continuous Condition
Notes: 1. "+" sign shows the direction of current flowing into the IC and "-" sign shows the current flowing out from the IC. 2. The low impedance voltage supply should not be applied to the OVP terminal.
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M51996AP/AFP
Electrical Characteristics
(VCC = 18 V, Ta = 25C, unless otherwise noted)
Block Supply voltage/ circuit current Item Operating supply voltage range Operation start up voltage Operation stop voltage VCC(START), VCC(STOP) difference Stand-by current Symbol VCC VCC(START) VCC(STOP) VCC ICCL Min. VCC(STOP) 15.2 9.0 5.0 65 50 7.3 8 1.3 140 -2.1 -0.9 -1.35 Limits Typ. -- 16.2 9.9 6.3 100 100 11 12 2.0 210 -1.5 -0.6 -0.99 Max. 30 17.2 10.9 7.6 150 200 17 19 3.0 320 -1.0 -0.4 -0.70 Unit V V V V A Test Conditions
VCC = VCC(START) - VCC(STOP) VCC = 14.5 V, Ta = 25C VCC = 14.5 V, -30 Ta 85C VCC = 15 V, f = 188 kHz VCC = 30 V, f = 188 kHz VCC = 25 V VCC = 9.5 V F/B terminal input current F/B terminal input current IFB = IFBMIND - IFBMAXD
Operating circuit current Circuit current in OVP state F/B Current at 0% duty Current at maximum duty Current difference between max and 0% duty F/B terminal voltage OVP terminal resistance OVP terminal H threshold voltage OVP terminal hysteresis voltage OVP terminal threshold current OVP terminal input current OVP reset supply voltage Difference supply voltage between operation stop and OVP reset Current from OVP terminal for OVP reset CLM+ CLM+ terminal threshold voltage CLM+ terminal current Delay time from CLM+ to VOUT
ICCO ICCOVP IFBMIND IFBMAXD IFB
mA mA A mA mA mA
VFB RFB VTHOVPH VTHOVP ITHOVP IINOVP VCCOVPC VCC(STOP) - VCCOVPC
4.9 420 540 -- 80 80 7.5 0.55
5.9 600 750 30 150 150 9.0 1.20
7.1 780 960 -- 250 250 10.0 --
V mV mV A A V V
F/B terminal input current = 0.95 mA
OVP
VTHOVP = VTHOVPH - VTHOVPL
VOVP = 400 mV OVP terminal is open. (high impedance)
ITHOVPC VTHCLM+ IINCLM+ TPDCLM+
-480 -210 180 -280 --
-320 -140 200 -200 150
-213 -93 220 -140 --
A mV A ns
VCC = 30 V VCC = 18 V
VCLM+ = 0 V
REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 5 of 35
M51996AP/AFP (VCC = 18 V, Ta = 25C, unless otherwise noted)
Block Oscillator Item Oscillating frequency Maximum ON duty Upper limit voltage of oscillation waveform Lower limit voltage of oscillation waveform Voltage difference between upper limit and lower limit of OSC waveform T-ON terminal voltage SOFT T-OFF terminal voltage Oscillating VSOFT = frequency 5.5 V during VSOFT = SOFT 2.5 V operation VSOFT = 0.2 V SOFT terminal input current SOFT terminal discharging current REG Output Regulator output voltage Output low voltage ISOFTIN ISOFDIS -0.5 1 -0.1 3.3 -- -- A mA VSOFT = 1 V Discharge current of SOFT terminal at VCC less than VCC(STOP) Symbol fOSC TDUTY VOSCH VOSCL VOSC Min. 170 47 3.97 1.76 2.11 Limits Typ. 188 50 4.37 1.96 2.41 Max. 207 53 4.77 2.16 2.71 Unit kHz % V V V Test Conditions RON = 20 k, ROFF = 17 k CF = 220 pF, -5 Ta 85C RON = 20 k, ROFF = 17 k CF = 220 pF
VT-ON VT-OFF fOSCSOFT
3.8 2.9 170 111 19.0
4.5 3.5 188 131 23.3
5.4 4.2 207 151 27.0
V V kHz
RON = 20 k ROFF = 17 k RON = 20 k, ROFF = 17 k CF = 220 pF
VREG VOL1 VOL2 VOL3
6.8 -- -- -- -- 16.0 15.5 -- -- 2.4 -- 30
7.8 0.04 0.7 0.85 1.3 16.7 16.5 60 40 2.5 1.0 40
8.8 0.4 1.4 1.0 2.0 -- -- -- -- 2.6 3.0 --
V V V V V V V ns ns V A dB VDET = 2.5 V VCC = 18 V, IO = 10 mA VCC = 18 V, IO = 100 mA VCC = 5 V, IO = 1 mA VCC = 5 V, IO = 100 mA VCC = 18 V, IO = -10 mA VCC = 18 V, IO = -100 mA
Output high voltage Output voltage rise time Detection Output voltage fall time Detection voltage DET terminal input current Voltage gain of detection amp
VOL4 VOH1 VOH2 TRISE TFALL VDET IINDET GAVDET
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M51996AP/AFP
Main Characteristics
Thermal Derating (Maximum Rating)
1800 16 m
Circuit Current vs. Supply Voltage (Normal Operation)
RON = 18 k fOSC = 500 kHz 14 m ROFF = 20 k
Power Dissipation Pd (mW)
Circuit Current ICC (A)
1500 1200 900 600 300 0 0 25 50 75 85 100 125 150
12 m 10 m fOSC = 100 kHz 150 100 50 0 0 10 20 Ta = 25 C Ta = 85 C Ta = -30 C 30 40
Ambient Temperature Ta (C)
Supply Voltage VCC (V)
SOFT Terminal Input Voltage VSOFT (V)
SOFT Terminal Input Voltage VSOFT (V)
SOFT Terminal Input Voltage vs. Expansion Rate of Period
5.0 (fOSC = 100 kHz)
(1) RON = 15 k, ROFF = 27 k (2) RON = 18 k, ROFF = 24 k (3) RON = 22 k, ROFF = 22 k (4) RON = 24 k, ROFF = 20 k (5) RON = 22 k, ROFF = 12 k (6) RON = 36 k, ROFF = 6.2 k
SOFT Terminal Input Voltage vs. Expansion Rate of Period
5.0 (fOSC = 500 kHz)
(1) RON = 15 k, ROFF = 27 k (2) RON = 18 k, ROFF = 24 k (3) RON = 22 k, ROFF = 22 k (4) RON = 24 k, ROFF = 20 k (5) RON = 22 k, ROFF = 12 k (6) RON = 36 k, ROFF = 6.2 k
4.0
4.0
3.0
3.0
2.0
(2)
2.0
(2) (3) (4)
1.0
(1) (3) (4) (5) (6)
1.0
(1)
(5)
(6)
0 0
2
4
6
8 10 12 14 16 18 20
0 0
2
4
6
8 10 12 14 16 18 20
Expansion Rate of Period (Times)
Expansion Rate of Period (Times)
SOFT Terminal Input Current ISOFTIN (nA)
-90 -80 -70 -60 -50 -40 -30 -20 -10 0 0 1 2 3 4 5 6
Ta = 25 C Ta = 85 C Ta = -30 C
CLM+ Terminal Threshold Voltage VTHCLM+ (mV)
-100
SOFT Terminal Input Current vs. Input Voltage
CLM+ Terminal Threshold Voltage vs. Ambient Temperature
210
205
200
195
7
8
9 10
190 -60 -40 -20
0
20
40
60
80 100
SOFT Terminal Input Voltage VSOFT (V)
Ambient Temperature Ta (C)
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M51996AP/AFP
CLM+ Terminal Current vs. CLM+ Terminal Voltage
400
CLM+ Terminal Current IINCLM+ (A)
REG Output Voltage vs. Ambient Temperature
REG Output Voltage VREG (V)
8.5 RC = RC = 3.6 k RC = 1.5 k
Ta = 25 C Ta = 85 C Ta = -30 C
300
8.0
200
7.5
100
0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
7.0 -60 -40 -20 0
20
40
60
80 100
CLM+ Terminal Voltage VCLM+ (V)
Ambient Temperature Ta (C)
Output High Voltage vs. Source Current
Output High Voltage VCC-VOH (V)
4.5 VCC = 18 V 4.2 Ta = 25C 3.9 3.6 3.3 3.0 2.7 2.4 2.1 1.8 1.5 1.2 10-3
3
Output Low Voltage vs. Sink Current
5.0
Output Low Voltage VOL (V)
4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5
Ta = 25C
VCC = 18 V VCC = 5 V
10-2
3
10-1
3
100
3
101
0 10-3
3
10-2
3
10-1
3
100
3
101
Source Current IOH (A)
Sink Current IOL (A)
Detection Terminal Input Current IINDET (A)
Detection Voltage vs. Ambient Temperature
2.55
Detection Terminal Input Current vs. Ambient Temperature
1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0 -60 -40 -20 0 20 40 60 80 100
Detection Voltage VDET (V)
2.50
2.45
2.40 -60 -40 -20
0
20
40
60
80 100
Ambient Temperature Ta (C)
Ambient Temperature Ta (C)
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M51996AP/AFP
Voltage Gain of Detection AMP vs. Frequency
50 45 40 40 50 (fOSC = 100 kHz) RON = 18 k ROFF = 20 k Ta = 25 C Ta = 85 C Ta = -30 C
Voltage Gain of Detection AMP GDET (dB)
ON Duty vs. F/B Terminal Input Current
30 25 20 15 10 5 0 102
3
ON Duty (%)
103
3
35
30
20
10
104
3
105
3
106
0 0 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
Frequency f (Hz)
F/B Terminal Input Current IF/B (mA)
ON Duty vs. F/B Terminal Input Current
50 (fOSC = 200 kHz) RON = 18 k ROFF = 20 k Ta = 25 C Ta = 85 C Ta = -30 C 50
ON Duty vs. F/B Terminal Input Current
(fOSC = 500 kHz) RON = 18 k ROFF = 20 k Ta = 25 C Ta = 85 C Ta = -30 C
40
40
ON Duty (%)
ON Duty (%)
30
30
20
20
10
10
0 0 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
0 0 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
F/B Terminal Input Current IF/B (mA)
F/B Terminal Input Current IF/B (mA)
Upper & Lower Limit Voltage of OSC vs. Ambient Temperature
Upper & Lower Limit Voltage of OSC VOSCH, VOSCL (V)
RON = 18 k 5.2 ROFF = 20 k 4.8 4.4 4.0 fOSC = 500 kHz fOSC = 200 kHz fOSC = 100 kHz fOSC = 100 kHz fOSC = 200 kHz fOSC = 500 kHz
Oscillating Frequency vs. CF Terminal Capacitance
Oscillating Frequency fOSC (kHz)
104
3
103
3
102
3
RON = 22 k ROFF = 12 k RON = 36 k ROFF = 6.2 k RON = 24 k ROFF = 20 k
2.2 2.0 1.8 -60 -40 -20 0 20
101
3
40
60
80 100
100 0 10
3
101
3
102
3
103
3
104
Ambient Temperature Ta (C)
CF Terminal Capacitance (pF)
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Oscillator Frequency vs. Ambient Temperature
120
ON Duty vs. ROFF
100 90 80
RON = 75 k
51 k 36 k 24 k 22 k 18 k 15 k 10 k
Oscillator Frequency fOSC (kHz)
RON = 24 k ROFF = 20 k CF = 330 pF
ON Duty (%)
70 60 50 40 30 20 10 0 100
3 5 7 101
110
100
90
3
5 7 102
80 -60 -40 -20
0
20
40
60
80 100
ROFF (k)
Ambient Temperature Ta (C)
Oscillator Frequency vs. Ambient Temperature
700
ON Duty vs. Ambient Temperature
100 90 80 (fOSC = 100 kHz)
RON = 36 k, ROFF = 6.2 k RON = 22 k, ROFF = 12 k RON = 24 k, ROFF = 20 k
Oscillator Frequency fOSC (kHz)
600
RON = 24 k ROFF = 20 k CF = 47 pF
500
ON Duty (%)
70 60 50 40 30 20 10
400
300
RON = 22 k, ROFF = 22 k RON = 18 k, ROFF = 24 k RON = 15 k, ROFF = 27 k
200 -60 -40 -20
0
20
40
60
80 100
0 -60 -40 -20
0
20
40
60
80 100
Ambient Temperature Ta (C)
Ambient Temperature Ta (C)
ON Duty vs. Ambient Temperature
100 90 80 (fOSC = 200 kHz)
RON = 36 k, ROFF = 6.2 k RON = 22 k, ROFF = 12 k RON = 24 k, ROFF = 20 k
ON Duty vs. Ambient Temperature
100 90 80 (fOSC = 500 kHz)
RON = 36 k, ROFF = 6.2 k RON = 22 k, ROFF = 12 k RON = 24 k, ROFF = 20 k
ON Duty (%)
ON Duty (%)
70 60 50 40 30 20 10
70 60 50 40 30 20 10
RON = 22 k, ROFF = 22 k RON = 18 k, ROFF = 24 k RON = 15 k, ROFF = 27 k
RON = 22 k, ROFF = 22 k RON = 18 k, ROFF = 24 k RON = 15 k, ROFF = 27 k
0 -60 -40 -20
0
20
40
60
80 100
0 -60 -40 -20
0
20
40
60
80 100
Ambient Temperature Ta (C)
Ambient Temperature Ta (C)
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M51996AP/AFP
OVP Terminal Input Current vs. Input Voltage
1m
OVP Terminal Input Current IOVP (A)
OVP Terminal Threshold Voltage vs. Ambient Temperature
1.1
OVP Terminal Threshold Voltage VTHOVP (V)
Ta = 25 C Ta = 85 C Ta = -30 C
VCC = 18 V
1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 -40 -20 0 20 40 60 80 100 L threshold voltage (VTHOVPL) H threshold voltage (VTHOVPH)
100
10
1
0.2
0.4
0.6
0.8
1.0
OVP Terminal Input Voltage VOVP (V)
Ambient Temperature Ta (C)
Current from OVP Terminal for OVP Reset ITHOVPC (A)
Circuit Current vs. Supply Voltage (OVP Operation)
8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0 0 10 20 30 40 OVP reset point 8.87 V (-30 C) 8.94 V (25 C) 9.23 V (85 C) Ta = 25 C Ta = 85 C Ta = -30 C
Current from OVP Terminal for OVP Reset vs. Supply Voltage
800 700 600 500 400 300 200 100 0 0 5 10 15 20 25 30 35 40 Ta = 25 C Ta = 85 C Ta = -30 C
Circuit Current ICC (mA)
Supply Voltage VCC (V)
Supply Voltage VCC (V)
Output Through Current Waveform at Rising Edge of Output Pulse
Output Through Current Waveform at Falling Edge of Output Pulse
Horizontal-axis: 20 ns/div Vertical-axis: 50 mA/div
Horizontal-axis: 20 ns/div Vertical-axis: 5 mA/div
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M51996AP/AFP
Application Example
(1) Application Example for Feed Forward Regulator
Rush current prevention circuit
+
R1
DC output
VCC REG
Line filter
Collector VOUT CLM+
R
AC input
+
CFIN R2
+
CVCC
M51996A
SOFT
Emitter GND
DET OVP F/B T-ON CF T-OFF
+
RON CF ROFF Feedback
OVP (TL431)
(2) Application Example for Fly-back Regulator
Rush current prevention circuit
+
R1
DC output
R21 RFB CFB
VCC F/B
Collector VOUT CLM+
R
Line filter
AC input
+
+
DET REG
R22
CFIN CVCC
M51996A
Emitter GND OVP
RNF
SOFT T-ON CF T-OFF
CNF RON CF ROFF
RCLM
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M51996AP/AFP
Function Description
Type M51996AP and M51996AFP are especially designed for off-line primary PWM control IC of switching mode power supply to get DC voltage from AC power supply. Using this IC, smart SMPS can be realized with reasonable cost and compact size as the number of external electric parts can be reduced and also parts can be replaced by reasonable one. In the following circuit diagram, MOS FET is used for output transistor, however bipolar transistor can be replaced with no problem.
Start-up Circuit Section The start-up current is such low current level as typical 100 A, as shown in figure 1, when the VCC voltage is increased from low level to start-up voltage VCC(START). In this voltage range, only a few parts in this IC, which has the function to make the output voltage low level, is alive and ICC current is used to keep output low level. The large voltage difference between VCC(START) and VCC(STOP) makes start-up easy, because it takes rather long duration from VCC(START) to VCC(STOP).
Circuit Current ICC (mA)
ICCO 11 mA
ICCL 100 A VCC VCC (STOP) (START) 9.9 V 16.2 V
Supply Voltage VCC (V)
Figure 1 Circuit Current vs. Supply Voltage
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M51996AP/AFP Oscillator Section The oscillation waveform is the triangle one. The ON-duration of output pulse depends on the rising duration of the triangle waveform and dead-time is decided by the falling duration. The rising duration is determined by the product of external resistor RON and capacitor CF and the falling duration is mainly determined by the product of resistor ROFF and capacitor CF.
VOSCH 4.4 V VOSCL 2.0 V
Waveform of CF terminal
Waveform of VOUT terminal in Max ON duty condition
VOH VOL
Figure 2 OSC. Waveform at Normal Condition (no-operation of intermittent action and OSC control circuit) 1. Oscillator operation when SOFT circuit does not operate Figure 3 shows the equivalent charging and discharging circuit diagram of oscillator. The current flows through RON from the constant voltage source of 5.8 V. CF is charged up by the same amplitude as RON current, when internal switch SW1, SW2 is switched to "charging side". The rise rate of CF terminal is given as
VT-ON RON x CF (V/s) ................................................ (1)
where VT-ON 4.5 V The maximum on duration is approximately given as
(VOSCH - VOSCL) x RON x CF VT-ON (s) ..................... (2)
where VOSCH 4.4 V VOSCL 2.0 V CF is discharged by the summed-up of ROFF current and one sixteenth (1/16) of RON current by the function of Q2, Q3 and Q4 when SW1, SW2 are switched to "discharge side". So fall rate of CF terminal is given as
VT-OFF ROFF x CF + VT-ON 16 x RON x CF (V/s) ..................... (3)
The minimum off duration approximately is given as
(VOSCH - VOSCL) x CF VT-OFF ROFF + VT-ON 16 x RON (s) ........................ (4)
The cycle time of oscillation is given by the summation of equations 2 and 4. The frequency including the dead-time is not influenced by the temperature because of the built-in temperature compensating circuit.
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M51996AP/AFP
5.8 V Q4 1/16 T-ON RON T-OFF ROFF CF CF Q2 Discharging From VF signal Vz = 4.2 V SW2 Switched by charging and discharging signal Q3 Q1 Charging SW1
M51996A
Figure 3 Schematic Diagram of Charging and Discharging Control Circuit for OSC Capacitor CF 2. Oscillator operation when the SOFT (soft start) circuit is operating. Output transistor is protected from rush current by CLM function at the start time of power on. SOFT terminal is used to improve the rising response of the output voltage of power supply (prevention of overshooting). The ON duration of output is kept constant, and the OFF duration is extended as the SOFT terminal voltage becomes lower by the soft start circuit of this IC. The maximum value of extension is set internally at approximately sixteen times of the maximum ON duration. The features of this method are as follows : (1) It is ideal for primary control as IC driving current is supplied from the third winding of the main transformer at the start-up because constant ON duration is obtained from start-up. (2) It is possible to get a wide dynamic range for ON/OFF ratio by pulse-by-pulse current limit circuit. (3) The response characteristics at power-on is not affected by input voltage as the pulse-by-pulse limit current value is not affected by the input voltage. Figure 4 shows the circuit diagram of the soft start. If SOFT terminal voltage is low, T-OFF terminal voltage becomes low and VT-OFF in equations (3) and (4) become low.
To REG Terminal To REG Terminal
RSOFT SOFT terminal CSOFT T-OFF terminal Vz 4.2 V Discharging transistor Note IC's internal circuit Note: Active when operation stops. GND terminal
Figure 4 Circuit Diagram of SOFT Terminal Section and T-OFF Terminal Section
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M51996AP/AFP
Waveform of CF terminal
VOSCH 4.4 V VOSCL 2.0 V t
Waveform of VOUT terminal in Max ON duty condition
VOH VOL t
Figure 5 Oscillator Waveform When the SOFT Circuit is Operating
Start from 0 V VOSCH Voltage waveform of CF Terminal VOSCL 0 t
The first output pulse Waveform of VOUT terminal in Max ON duty condition VOH No output pulse t Operation start
VOL 0
Figure 6 Relationship Between Oscillator Waveform and Output Waveform at Start-up Figure 5 shows the relationship between oscillator waveform and output pulse. If the SOFT terminal voltage is VSOFT, the rise rate of CF terminal given as
VT-ON RON x CF (V/s) ................................................ (5)
The fall rate of oscillation waveform is given as
VSOFT - VBE ROFF x CF + VT-ON 16 x RON x CF (V/s) ..................... (6)
Where VSOFT ; SOFT terminal applied voltage VBE 0.65 V If VSOFT - VBE < 0, VSOFT - VBE = 0 If VSOFT - VBE > VT-OFF ( 3.5 V), VSOFT - VBE = VT-OFF
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M51996AP/AFP PWM Comparator, PWM Latch and Current Limit Latch Section Figure 7 shows the schematic diagram of PWM comparator and PWM latch section. The on-duration of output waveform coincides with the rising duration of CF terminal waveform, when the no output current flows from F/B terminal. When the F/B terminal has finite impedance and current flows out from F/B terminal, "A" point potential shown in figure 7 depends on this current. So the "A" point potential is close to GND level when the flow-out current becomes large. "A" point potential is compared with the CF terminal oscillator waveform and PWM comparator, and the latch circuit is set when the potential of oscillator waveform is higher than "A" point potential. The latch circuit is reset during the dead-time of oscillation (falling duration of oscillation current). So the "B" point potential or output waveform of latch circuit is the one shown in figure 8. The final output waveform or "C" point potential is got by combining the "B" point signal and dead-time signal logically. (please refer to figure 8)
7.1 V 5.8 V
500 15.2 k 3k
Point A
200 A
6S F/B
1S
- +
PWM COMP.
Latch current
Point B To output
*1 Point C
Point D
*2 CLM+
M51996A
From OSC
CF
Notes: 1. Resistor to determine current limit sensitivety 2. High level during dead time
Figure 7 PWM Comparator PWM Latch and Current Limit Latch Section
OSC waveform Waveform at point A
Waveform of OSC & point A
Point B Point C
Figure 8 Waveforms of PWM Comparator Input Point A, Latch Circuit Points B and C
REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 17 of 35
M51996AP/AFP When the current-limit signal is applied before the crossing instant of "A" pint potential and CF terminal voltage shown in figure 7, this signal makes the output "off" and the off state will continue until next cycle. Figure 9 shows the timing relation among them. If the current limiting circuit is set, no waveform is generated at output terminal, however this state is reset during the succeeding dead-time. So this current limiting circuit is able to have the function in every cycle, and is named "pulse-by-pulse current limit". There happen some noise voltage on RCLM during the switching of power transistor due to the snubber circuit and stray capacitor of the transformer windings.
OSC waveform of CF terminal Waveform of CLM+ terminal
VTHCLM 200 mV
Current limit signal to set latch
Waveform of VOUT terminal
Figure 9 Operating Waveform of Current Limiting Circuit To eliminate the abnormal operation by the noise voltage, the low pass filter, which consists of RNF and CNF is used as shown in figure 10. It is recommended to use 10 to 100 for RNF because such range of RNF is not influenced by the flow-out current of some 200 A from CLM+ terminal and CNF is designed to have the enough value to absorb the noise voltage.
M51996A
VOUT
Point D
CLM+
RNF CNF RCLM+
GND
Figure 10 Connection Diagram of Current Limit Circuit
REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 18 of 35
M51996AP/AFP Voltage Detector Circuit (DET) Section The DET terminal can be used to control the output voltage which is determined by the winding ratio of fly back transformer in fly-back system or in case of common ground circuit of primary and secondary in feed forward system. The circuit diagram is quite similar to that of shunt regulator type 431 as shown in figure 11. As well known from figure 11 and figure 12, the output of OP AMP has the current-sink ability, when the DET terminal voltage is higher than 2.5 V. But it becomes high impedance state when lower than 2.5 V DET terminal and F/B terminal have inverting phase characteristics each other, so it is recommended to connect the resistor and capacitor in series between them for phase compensation. It is very important one can not connect by resistor directly as there is the voltage difference between them and the capacitor has the DC stopper function.
7.1 V
3k 1S 500 6S F/B DET 5.4 k
10.8 k
10.8 k
10 S 1.2 k
Figure 11 Voltage Detector Circuit Section (DET)
7.1 V
3k 500
1S
6S F/B
OP AMP
- +
2.5 V
DET
Figure 12 Schematic Diagram of Voltage Detector Circuit Section (DET)
REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 19 of 35
M51996AP/AFP OVP Circuit (Over Voltage Protection Circuit) Section OVP circuit is basically positive feedback circuit constructed by Q2, Q3 as shown in figure 13. Q2, Q3 turn on and the circuit operation of IC stops, when the input signal is applied to OVP terminal. (threshold voltage 750 mV) The current value of I2 is about 150A when the OVP does not operates but it decreases to about 2 A when OVP operates. It is necessary to input the sufficient larger current (800 A to 8 mA) than I2 for triggering the OVP operation. The reason to decrease I2 is that it is necessary that ICC at the OVP rest supply voltage is small. It is necessary that OVP state holds by circuit current from R1 in the application example, so this IC has the characteristic of small ICC at the OVP reset supply voltage ( stand-by current + 20 A) On the other hand, the circuit current is large in the higher supply voltage, so the supply voltage of this IC doesn't become so high by the voltage drop across R1. This characteristic is shown in figure 14. The OVP terminal input current in the voltage lower than the OVP threshold voltage is based on I2 and the input current in the voltage higher than the OVP threshold voltage is the sum of the current flowing to the base of Q3 and the current flowing from the collector of Q2 to the base. For holding in the latch state, it is necessary that the OVP terminal voltage is kept in the voltage higher than VBE of Q3. So if the capacitor is connected between the OVP terminal and GND, even though Q2 turns on in a moment by the surge voltage, etc, this latch action does not hold if the OVP terminal voltage does not become higher than VBE of Q3 by charging this capacitor. For resetting OVP state, it is necessary to make the OVP terminal voltage lower than the OVP L threshold voltage or make VCC lower than the OVP reset supply voltage. As the OVP reset voltage is settled on the rather high voltage of 9.0 V, SMPS can be reset in rather short time from the switch-off of the AC power source if the smoothing capacitor is not so large value.
VCC 7.8 V 8k 12 k 100 A I1 Q1
Q2 400 OVP 2.5 k GND I2 Q3
Note: I1 = 0 when OVP operates
Figure 13 Detail Diagram of OVP Circuit
REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 20 of 35
M51996AP/AFP
8
Circuit Current ICC (mA)
OVP reset point 7 8.87 V (-30 C) 8.94 V (25 C) 6 9.23 V (85 C) 5 4 3 2 1 0 0 5 10 15 20 25 30 35 40 Ta = 25 C Ta = 85 C Ta = -30 C
Supply Voltage VCC (V)
Figure 14 Circuit Current vs. Supply Voltage (OVP Operation)
Output Section It is required that the output circuit have the high sink and source abilities for MOS FET drive. It is well known that the "totempole circuit has high sink and source ability. However, it has the demerit of high through current. For example, the through current may reach such the high current level of 1 A, if type M51996A has the "conventional" totempole circuit. For the high frequency application such as higher than 100 kHz, this through current is very important factor and will cause not only the large ICC current and the inevitable heat-up of IC but also the noise voltage. This IC uses the improved totempole circuit, so without deteriorating the characteristic of operating speed, its through current is approximately 100 mA.
REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 21 of 35
M51996AP/AFP
Application Note of Type M51996AP/AFP
Design of Start-up Circuit and The Power Supply of IC 1. The start-up circuit when it is not necessary to set the start and stop input voltage
Rectified DC voltage from smoothing capacitor R1 VF Third winding of bias winding + M51996A CVCC Main transformer
VCC
GND
Figure 15 Start-up Circuit Diagram When it is Not Necessary to Set The Start and Stop Input Voltage Figure 15 shows one of the example circuit diagram of the start-up circuit which is used when it is not necessary to set the start and stop voltage. It is recommended that the current more than 300 A flows through R1 in order to overcome the operation start-up current ICC(START) and CVCC is in the range of 10 to 47 F. The product of R1 by CVCC causes the time delay of operation, so the response time will be long if the product is too much large. Just after the start-up, the ICC current is supplied from CVCC, however, under the steady state condition, IC will be supplied from the third winding or bias winding of transformer, the winding ratio of the third winding must be designed so that the induced voltage may be higher than the operation-stop voltage VCC(STOP). The VCC voltage is recommended to be 12 V to 17 V as the normal and optimum gate voltage is 10 to 15 V and the output voltage (VOH) of type M51996AP/AFP is about (VCC - 2 V). It is not necessary that the induced voltage is settled higher than the operation start-up voltage VCC(START), and the high gate drive voltage causes high gate dissipation, on the other hand, too low gate drive voltage does not make the MOS FET fully on-state or the saturation state. 2. The start-up circuit when it is not necessary to set the start and stop input voltage It is recommend to use the third winding of "forward winding" or "positive polarity" as shown in figure 16, when the DC source voltages at both the IC operation start and stop must be settled at the specified values. The input voltage (VIN(START)), at which the IC operation starts, is decided by R1 and R2 utilizing the low start-up current characteristics of type M51996AP/AFP. The input voltage (VIN(STOP)), at which the IC operation stops, is decided by the ratio of third winding of transformer. The VIN(START) and VIN(STOP) are given by following equations.
VIN (START) R1 x ICCL + ( R1 + 1) x VCC (START) ......... (7) R2
VIN (STOP) (VCC (STOP) - VF) x
NP 1 + V'IN RIP (P-P) ...... (8) NB 2
Where ICCL is the operation start-up current of IC VCC(START) is the operation start-up voltage of IC VCC(STOP) is the operation stop voltage of IC VF is the forward voltage of rectifier diode V'IN(P-P) is the peak to peak ripple voltage of
VCC terminal NB V'IN RIP (P-P) NP
It is required that the VIN(START) must be higher than VIN(STOP).
REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 22 of 35
M51996AP/AFP When the third winding is the "fly back winding" or "reverse polarity", the VIN(START) can be fixed, however, VIN(STOP) can not be settled by this system, so the auxiliary circuit is required.
Rectified DC voltage from smoothing capacitor
VIN R1
NP
Primary winding of transformer
VCC
VF NB + CVCC
Third winding of transformer
M51996A
R2
GND
Figure 16 Start-up Circuit Diagram When It is Not Necessary to Set The Start and Stop Input Voltage 3. Notice to the VCC, VCC line and GND line
Collector
VCC
Main transformer third winding + CVCC
M51996A
Output RCLM Emitter GND
Figure 17 How to Design The Conductor-pattern of Type M51996A on PC Board (schematic example) To avoid the abnormal IC operation, it is recommended to design the VCC is not vary abruptly and has few spike voltage, which is induced from the stray capacity between the winding of main transformer. To reduce the spike voltage, the CVCC, which is connected between VCC and ground, must have the good high frequency characteristics. To design the conductor-pattern on PC board, following cautions must be considered as shown in figure 17. (1) To separate the emitter line of type M51996A from the GND line of the IC (2) The locate the CVCC as near as possible to type M51996A and connect directly (3) To separate the collector line of type M51996A from the VCC line of the IC (4) To connect the ground terminals of peripheral parts of ICs to GND of type M51996A as short as possible
REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 23 of 35
M51996AP/AFP 4. Power supply circuit for easy start-up When IC start to operate, the voltage of the CVCC begins to decrease till the CVCC becomes to be charged from the third winding of main-transformer as the ICC of the IC increases abruptly. In case shown in figure 15 and 16, some "unstable start-up" or "fall to start-up" may happen, as the charging interval of CVCC is very short duration; that is the charging does occur only the duration while the induced winding voltage is higher than the CVCC voltage, if the induced winding voltage is nearly equal to the "operation-stop voltage" of type M51996A. It is recommended to use the 10 to 47 F for CVCC1, and about 5 times capacity bigger than CVCC1 for CVCC2.
R1 Main transformer third winding +
CVCC1 CVCC2
VCC
M51996A
+
GND
Figure 18 DC Source Circuit for Stable Start-up
REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 24 of 35
M51996AP/AFP OVP Circuit 1. To avoid the miss operation of OVP It is recommended to connect the capacitor between OVP terminal and GND for avoiding the miss operation by the spike noise. The OVP terminal is connected with the sink current source ( 150 A) in IC when OVP does not operate, for absorbing the leak current of the photo coupler in the application. So the resistance between the OVP terminal and GND for leak-cut is not necessary. If the resistance is connected, the supply current at the OVP reset supply voltage becomes large. As the result, the OVP reset supply voltage may become higher than the operation stop voltage. In that case, the OVP action is reset when the OVP is triggered at the supply voltage a little high than the operation stop voltage. So it should be avoided absolutely to connect the resistance between the OVP terminal and GND.
To REG or VCC VCC 5.6 k
M51996A OVP GND +
Photo coupler
Figure 19 Peripheral Circuit of OVP Terminal 2. Application circuit to make the OVP-reset time fast The reset time may becomes problem when the discharge time constant of CFIN * (R1 + R2) is long. Under such the circuit condition, it is recommend to discharge the CVCC forcedly and to make the VCC low value; This makes the OVP-reset time fast.
To main transformer R1
+ CFIN R2
+ CVCC VCC M51996A GND
The time constant of this part should be short
Figure 20 Example Circuit Diagram to Make The OVP-reset-time Fast
REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 25 of 35
M51996AP/AFP 3. OVP setting method using the induced third winding voltage on fly back system For the over voltage protection (OVP), the induced fly back type third winding voltage can be utilized, as the induced third winding voltage depends on the output voltage. Figure 21 shows one of the example circuit diagram.
Main transformer third winding OVP 470 + CVCC GND
VCC
M51996A
Figure 21 OVP Setting Method Using The Induced Third Winding Voltage on Fly Back System 4. Method to control for ON/OFF using the OVP terminal You can reset OVP to lower the OVP terminal voltage lower than VTHOVPL. So you can control for ON/OFF using this nature. The application is shown in figure 22. The circuit turns off by SW OFF and turns on by SW ON in this application. Of course you can make use of the transistor or photo-transistor instead of SW.
REG 5.1 k
M51996A
ON/OFF SW
Figure 22 Method to Control for ON/OFF Using The OVP Terminal
REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 26 of 35
M51996AP/AFP Current Limiting Circuit 1. Peripheral circuit of CLM+ terminal Figure 23 shows the example circuit diagrams around the CLM+ terminal. It is required to connect the low pass filter, in order to reduce the spike current component, as the main current or drain current contains the spike current especially during the turn-on duration of MOS FET. 1,000 pF to 22,000 pF is recommended for CNF and the RNF1 and RNF2 have the function both to adjust the "currentdetecting-sensitivity" and to consist the low pass filter. To design the RNF1 and RNF2, it is required to consider the influence of CLM+ terminal source current (IINCLM+), which value is in the range of 90 to 270 A. In order to be not influenced from these resistor paralleled value of RNF1 and RNF2, (RNF1//RNF2) is recommended to be less than 100 . The RCLM should be the non-inductive resistor.
CFIN Input smoothing capacitor
+
R1
VCC
Collector VOUT
+
CVCC
M51996A CLM+ Emitter CNF RNF1 RNF2 RCLM
GND
Figure 23 Peripheral Circuit Diagram of CLM+ Terminal 2. Over current limiting curve (1) In case of feed forward system
I2 IP1 I1
CLM I1 RCLM
IP2 I2
(a) Feed forward system
(b) Primary and secondary current
Figure 24 Primary and Secondary Current Waveforms Under The Current Limiting Operation Condition on Feed Forward System Figure 24 shows the primary and secondary current wave-forms under the current limiting operation. At the typical application of pulse by pulse primary current detecting circuit, the secondary current depends on the primary current. As the peak value of secondary current is limited to specified value, the characteristics curve of output voltage versus output current become to the one as shown in figure 25. The demerit of the pulse by pulse current limiting system is that the output pulse width can not reduce to less than some value because of the delay time of low pass filter connected to the CLM+ terminal and propagation delay time TPDCLM from CLM+ terminal to output terminal of type M51996A. The typical TPDCLM+ is 100 ns. As the frequency becomes higher, the delay time must be shorter. And as the secondary output voltage becomes higher, the dynamic range of on-duty must be wider; it means that it is required to make the on-duration much more narrower. So this system has the demerit at the higher oscillating frequency and higher output voltage applications. To prevent that the SOFT terminal is used to lower the frequency when the curve starts to become vertical.
REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 27 of 35
M51996AP/AFP
Output Voltage
Output Current
Figure 25 Over Current Limiting Curve on Feed Forward System If the curve becomes vertical because of an excess current, the output voltage is lowered and no feedback current flows from feedback photo-coupler; the PWM comparator operates to enlarge the duty sufficiently, but the signal from the CLM+ section operates to make the pulse width narrower. Under the condition in which I2 in figure 24 does not become 0, the output voltage is proportional to the product of the input voltage VIN (primary side voltage of the main transformer) and on duty. If the bias winding is positive, VCC is approximately proportional to VIN. The existence of feed back current of the photo-coupler is known by measuring the F/B terminal voltage which becomes less than 2VBE in the internal circuit of REG terminal and F/B terminal if the output current flows from the F/B terminal.
REG
3k 1S 500 6S
F/B M51996A
Figure 26 Relationship Between REG Terminal and F/B Terminal Figure 27 shows an application example. Q1 is turned on when normal output voltage is controlled at a certain value. The SOFT terminal is clamped to a high-level voltage. If the output voltage decreases and the curve starts to drop, no feed back current flows, Q1 is turned off and the SOFT terminal responds to the smoothed output voltage. It is recommended to use an R1 and R2 of 10 k to 30 k. An R3 of 20 to 100 k and C of 1000 pF to 8200 pF should be used.
REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 28 of 35
M51996AP/AFP
D2 VCC Collector VOUT
+
CVCC
Bias winding of the main transformer
M51996A
SOFT
R3
To output transistor
C F/B R1 R2 Q1 D1 REG
Photo-coupler for feed back signal
Figure 27 Current to Lower Frequency During Over Current To change the knee point of frequency drop, use the circuit in figure 28.
VOUT SOFT VOUT SOFT VOUT SOFT
To make the knee point high
To make the knee point low
Figure 28 Method to Control The Knee Point of Frequency Drop To have a normal SOFT start function in the circuit in figure 27, use the circuit in figure 29. It is recommended to use an R4 of 10 k.
D2 VCC Collector VOUT
+ CVCC
Bias winding of the main transformer
M51996A
SOFT R4
R3 C
To output transistor
F/B R1
REG RSOFT Q2 CSOFT R2 Q1 D1
+
Photo-coupler for feed back signal
Figure 29 Circuit to Use Frequency Drop During The Over Current and Normal Soft Start
REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 29 of 35
M51996AP/AFP (2) In case of fly back system The DC output voltage of SMPS depends on the VCC voltage of type M51996A when the polarity of the third winding is negative and the system is fly back. So the operation of type M51996A will stop when the VCC becomes lower than "Operation-stop voltage" of M51996A when the DC output voltage of SMPS decreases under specified value at over load condition.
DC Output Voltage
Point that VCC voltage or third winding voltage decreases under "Operation-stop voltage"
DC Output Current
Figure 30 Over Current Limiting Curve on Fly Back System
VCC
Collector R3 + CVCC R4
M51996A
SOFT
F/B R1 R2
REG
To photo-coupler for feed back signal
Figure 31 Current to Lower The Frequency During The Over Current in The Fly Back System However, the M51996A will non-operate and operate intermittently, as the VCC voltage rises in accordance with the decrease of ICC current. The fly back system has the constant output power characteristics as shown in figure 30 when the peak primary current and the operating frequency are constant. To avoid an increases of the output current, the frequency is lowered when the DC output voltage of SMPS starts to drop using the SOFT terminal. VCC is divided and is input to the SOFT terminal as shown in figure 31, because the voltage in proportional to the output voltage is obtained from the bias winding. In this application example, the current flowing to R3 added to the start-up current. So please use high resistance or 100 k to 200 k for R3. The start-up current is not affected by R3 if R3 is connected to CVCC2 in the circuit shown in figure 18.
REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 30 of 35
M51996AP/AFP Output Circuit 1. The output terminal characteristics at the VCC voltage lower than the "Operation-stop" voltage The output terminal has the current sink ability even though the VCC voltage lower than the "Operation-stop" voltage or VCC(STOP) (It means that the terminal is "Output low state" and please refer characteristics of output low voltage versus sink current.) This characteristics has the merit not to damage the MOS FET at the stop of operation when the VCC voltage decreases lower than the voltage of VCC(STOP), as the gate charge of MOS FET, which shows the capacitive load characteristics to the output terminal, is drawn out rapidly. The output terminal has the draw-out ability above the VCC voltage of 2 V, however, lower than the 2V, it loses the ability and the output terminal potential may rise due to the leakage current. In this case, it is recommended to connect the resistor of 100 k between gate and source of MOS FET as shown in figure 32.
To main transformer VOUT
M51996A
100 k RCLM
Figure 32 Circuit Diagram to Prevent The MOS-FET Gate potential Rising 2. MOS FET gate drive power dissipation Figure 33 shows the relation between the applied gate voltage and the stored gate charge. In the region 1, the charge is mainly stored at CGS as the depletion is spread and CGD is small owing to the off-state of MOS FET and the high drain voltage. In the region 2, the CGD is multiplied by the "mirror effect" as the characteristics of MOS FET transfers from offstate to on-state. In the region 3, both the CGD and CGS affect to the characteristics as the MOS FET is on-state and the drain voltage is low.
20 Drain ID 15 VDS = 80 V 200 V 320 V (3) (2)
CGS
Gate-source Voltage VGS (V)
CGD Gate CDS VGS VD
10
5 (1)
ID = 4 A
0 0 4 8 12 16 20
Source
Total Stored Gate Charge QGSH (nC)
Figure 33 The Relation Between Applied Gate-source Voltage and Stored Gate Charge The charging and discharging current caused by this gate charge makes the gate power dissipation. The relation between gate drive current ID and total gate charge QGSH is shown by following equation;
ID = QGSH * fOSC ...................................................... (9)
Where fOSC is switching frequency
REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 31 of 35
M51996AP/AFP As the gate drive current may reach up to several tenths milliamperes at 500 kHz operation, depending on the size of MOS FET, the power dissipation caused by the gate current can not be neglected. In this case, following action will be considered to avoid heat up of type M51996A. (1) To attach the heat sink to type M51996A (2) To use the printed circuit board with the good thermal conductivity (3) To use the buffer circuit shown next section 3. Output buffer circuit It is recommended to use the output buffer circuit as shown in figure 34, when type M51996A drives the large capacitive load or bipolar transistor.
VOUT M51996A
Figure 34 Output Buffer Circuit Diagram
DET Circuit Figure 35 shows how to use the DET circuit for the voltage detector and error amplifier. For the phase shift compensation, it is recommended to connected the CR network between DET terminal and F/B terminal.
A C F/B C2 DET C4 R2 R3 B C1 R1 Detecting voltage
M51996A
Figure 35 How to Use The DET Circuit for The Voltage Detector Figure 36 shows the gain-frequency characteristics between point B and point C shown in figure 35.
GAVDET (DC voltage gain)
Log G (dB)
G1 1 2
Log
Figure 36 Gain-frequency Characteristics Between Point B and C Shown in Figure 35 The G1, 1 and 2 are given by following equations;
G1 = 1 = 2 = R3 ........................... (10) R1 / R2 1 .............................. (11) C2 * R3 C1 + C2 C1 * C2 * R3 ..................... (12)
REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 32 of 35
M51996AP/AFP At the start of the operation, there happen to be no output pulse due to F/B terminal current through C1 and C2, as the potential of F/B terminal rises sharply just after the start of the operation. Not to lack the output pulse, is recommended to connect the capacitor C4 as shown by broken line. Please take notice that the current flows through the R1 and R2 are superposed to ICC(START). Not to superpose, R1 is connected to CVCC2 as shown in figure 18. How to Get The Narrow Pulse Width During The Start of Operation Figure 37 shows how to get the narrow pulse width during the start of the operation. If the pulse train of forcedly narrowed pulse-width continues too long, the misstart of operation may happen, so it is recommended to make the output pulse width narrow only for a few pulse at the start of operation. 0.1 F is recommended for the C.
F/B M51996A 100 To photo coupler C
Figure 37 How to Get The Narrow Pulse Width During The Start of Operation
How to Synchronize with External Circuit Type M51996A has no function to synchronize with external circuit, however, there is some application circuit for synchronization as shown in figure 38.
M51996A T-ON CF T-OFF
RON
CF
ROFF Q1 Synchronous pulse
Oscillating waveform 0V
Synchronize waveform Minimum pulse width of synchronous pulse
0V Maximum pulse width of synchronous pulse
Figure 38 How to Synchronize With External Circuit
REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 33 of 35
M51996AP/AFP Driver Circuit for Bipolar Transistor When the bipolar transistor is used instead of MOS FET, the base current of bipolar transistor must be sinked by the negative base voltage source for the switching-off duration, in order to make the switching speed of bipolar transistor fast one. In this case, over current can not be detected by detecting resistor in series to bipolar transistor, so it is recommended to use the CT (current transformer).
VCC
VCC
Collector M51996A
VOUT
-VSS (-2 V to -5 V)
GND
Emitter
Figure 39 Driver Circuit Diagram (1) for Bipolar Transistor For the low current rating transistor, type M51996A can drive it directly as shown in figure 40.
VCC
Collector M51996A
VOUT Bipolar transistor
GND
Emitter
Figure 40 Driver Circuit Diagram (2) for Bipolar Transistor
Attention for Heat Generation The maximum ambient temperature of type M51996A is +85C, however the ambient temperature in vicinity of the IC is not uniform and varies place by place, as the amount of power dissipation is fearfully large and the power dissipation is generated locally in the switching regulator. So it is one of the good idea to check the IC package temperature. The temperature difference between IC junction and the surface of IC package is 15C or less, when the IC junction temperature is measured by temperature dependency of forward voltage of pin junction, and IC package temperature is measured by "thermo-viewer", and also the IC is mounted on the "phenol-base" PC board in normal atmosphere. So it is concluded that the maximum case temperature (surface temperature of IC) rating is 120C with adequate margin.
REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 34 of 35
M51996AP/AFP
Package Dimensions
JEITA Package Code P-SOP16-5.3x10.1-1.27 RENESAS Code PRSP0016DE-A Previous Code 16P2N-A MASS[Typ.] 0.2g
16
9
HE
*1
E
F
NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
1 Index mark
8 A2 A1
c
*2 D
Reference Symbol
Dimension in Millimeters
e
y
*3
bp
Detail F
D E A2 A1 A bp c HE e y L
Min Nom Max 10.0 10.1 10.2 5.2 5.3 5.4 1.8 0.1 0.2 0 2.1 0.35 0.4 0.5 0.18 0.2 0.25 0 8 7.5 7.8 8.1 1.12 1.27 1.42 0.1 0.4 0.6 0.8
A
JEITA Package Code P-DIP14-6.3x19-2.54
RENESAS Code PRDP0014AA-A
Previous Code 14P4
MASS[Typ.] 1.0g
14
8
1
7
*1
c
e1
E
*2
D
NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
A2
L
A
Reference Symbol
Dimension in Millimeters
e SEATING PLANE
*3
b3
bp
e1 D E A A1 A2 bp b3 c e L
Min Nom Max 7.32 7.62 7.92 18.8 19.0 19.2 6.15 6.3 6.45 4.5 0.51 3.3 0.4 0.5 0.6 1.4 1.5 1.8 0.22 0.27 0.34 0 15 2.29 2.54 2.79 3.0
REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 35 of 35
L
A1
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries.
RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
http://www.renesas.com
Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510
(c) 2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
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